1. Field of the Invention
The present invention relates to a wiring board for a semiconductor integrated circuit package and a semiconductor integrated circuit device using the wiring board. Particularly, it relates to a wiring board for a semiconductor integrated circuit package for mounting an LSI chip by flip-chip connection and to a semiconductor integrated circuit device in which an LSI chip is mounted on the wiring board.
2. Description of the Related Art
Recently, the number of pins and the frequency of an LSI have been increased. Accordingly, when forming an LSI package, there is a technique that is broadly used for flip-chip connecting the LSI to a package board. FIG. 1 is a plan view for showing an example of a connecting surface of an LSI between a package, which has bumps arranged in an area-array form. It is not possible to deal with the LSI with a large number of pins by a peripheral arrangement in which bumps are disposed only in the peripheral part of the connecting surface. Thus, when there are a large number of pins as shown in FIG. 1, there is employed a structure in which bumps 222 are disposed on the entire connecting surface of an LSI chip 221. On a package board to which the LSI chip with plane-arranged bumps is mounted, flip-chip pads (referred to as FC pads hereinafter) are arranged in an area-array form.
There have been proposed a structure of arrangement which allots a net of signals to the bumps of the outer periphery and allots nets of ground and power supply to the bumps on the inner side, when the bumps of LSI with large number of pins are arranged in an area-array form (for example, see Patent Documents 1, 2). One of the reasons for employing such bump arranging structure is that if the signal is allotted to the inner bumps, the number of columns for the signal pads is increased on the package board. Thus, it increases the number of wiring layers for enclosing signal wirings that connect the FC pads and BGA (ball grid array) land, thereby increasing the cost.
As a package board for flip-chip mounting the LSI chip shown in FIG. 1, it is considered preferable to employ a structure that disposes a ground plane (or a power supply plane) on the surface layer to which the LSI chip is mounted and disposes a signal wiring layer on the inner layer for stabilizing signal and suppressing signal leakage/interference. FIG. 2 and FIG. 3 show an example of the package board which is designed in view of such consideration. FIG. 2 is a cross section of a semiconductor integrated circuit device which is constituted by mounting the LSI chip on the package board, and FIG. 3 are top plan views of each wiring layer of the package board (In FIG. 2, there is only shown a right-half part since the package has a symmetrical structure). In FIG. 2, on a package board 200, the LSI chip 221 is mounted through the bumps 222. In the package board 200, five layers of wiring layers are stacked. The wiring layer to which the LSI chip is mounted is referred to as a first layer, and it ascends in order towards the lower side. Thus, the wiring layer to which a solder ball 223 is formed is referred to as a fifth layer. The first layer is provided with FC pads 206-208 and a ground plane 203 for installing the LSI chip 221, the second layer with a signal line 201, the third layer with a power supply plane 202, the fourth layer with a ground plane 204, and the fifth layer with lands 211-213 for mounting the solder ball 223. Wirings in each layer are connected by interlayer connecting conductors 209a-209g, which are formed by embedding via holes with a conductive material. For simplifying the drawing, the LSI chip 221 is illustrated with thirty-six pins, however, the number of pins actually used in the LSI reaches some hundreds to some thousands.
As shown in FIG. 3A, among the thirty-six FC pads, the outermost pad is allotted to the signal FC pad 208, the inner pads to an FC pad 206 and to a power supply FC pad 207. The path for the signal is connected from the signal FC pad 208 in the first layer to the second layer through the interlayer connecting conductor 209d, led to the peripheral part in the second layer by the signal wiring 201 as shown in FIG. 3B and, thereafter, brought to the land 213 of the fifth layer through the interlayer connecting conductor 209g. The signal line 201 is covered by the ground plane 203 and the power supply plane 202 from its top and bottom, thereby forming a strip line.
In the third layer where the power supply plane 202 is formed, as shown in FIG. 3C, there are formed an opening for letting through the interlayer connecting conductors 209a, 209e for ground and an opening for letting through the interlayer connecting conductor 209g for signals. Further, in the fourth layer where the ground plane 204 is formed, as sown in FIG. 3D, there are formed an opening for letting through the interlayer connecting conductor 209f for the power supply and an opening for letting through the interlayer connecting conductor 209g for the signals. In the fifth layer, as shown in FIG. 3E, the land 211 for the ground, the land 212 for the power supply, and the land 213 for the signals are arranged in an area-array form.
Like this example, as a way of determining allotment with respect to each wiring layer of the package board, it is advantageous to allot the ground plane or the power supply plane in the first layer and allot the signal wiring in the second layer or lower in terms of the electric property. The reason for this is that this arrangement provides a strip line structure in which the top and bottom of the signal wiring are covered by the power supply plane or the ground plane (hereinafter, “power supply or ground” is expressed as “power-supply/ground”). Thus, the transmission path suited for high-speed signal transmission can be formed and the signal wiring can be shielded. However, if the signal wiring is disposed on the first layer, the signal wiring is to be exposed. Thus, it may be affected by external noises or the characteristic impedance may be fluctuated by the influence of a ring that is mounted on the surface of the package board. Therefore, the electric property may be deteriorated. Therefore, in the case where a large number of wiring layers can be provided, the electric property can be improved by allotting the signal wiring on the second layer or lower but not on the first layer.
Further, with the structure where the power supply plane and the ground plane are provided adjacent to each other on the third layer and the fourth layer, a large capacity can be secured between the power supply and the ground.    Patent Document 1: Japanese Patent Unexamined Publication 2000-307005    Patent Document 2: Japanese Patent Unexamined Publication 2004-6513
However, there are following shortcomings in the above-described structure in which the signal is allotted to the FC pad in the outer peripheral part, the power supply and the ground are allotted to the inner FC pads, and the signal wiring is allotted in the second layer by disposing the power-supply/ground plane at the outer peripheral part of the LSI on the LSI mount surface.
The first shortcoming is that the signal property is deteriorated since the power-supply/ground plane on the first layer and the FC pad for the power-supply/ground of the LSI are disconnected by the signal FC pad. FIG. 4 is an enlarged view of the vicinity of the FC pads that are shown in FIG. 2. When signal current I sig is flown to the signal wiring 201 of the second layer, return currents I ret1 and I ret3 are generated in the ground plane 203 of the first layer as the upper layer thereof and the power supply plane 202 of the third layer as the lower layer. When a signal is flown between the LSI and the package board through the FC pads, the return current passes the power-supply/ground pad that is closest to the signal pad and flows between the LSI and the package board. However, the power-supply/ground plane (203) on the first layer is cut from the FC pad of the power-supply/ground in the vicinity of an end 203E of the plane. Thus, the return current flowing in the power-supply/ground plane of the first layer cannot flow directly to the FC pads of the power-supply/ground. Therefore, there generates mismatch in the characteristic impedance, thereby causing reflection of the signal or unnecessary radiation.
The second shortcoming is that the effect of decreasing the switching noise becomes insignificant since the power-supply/ground plane of the first layer and the FC pad for the power-supply/ground plane of the LSI are disconnected by the signal FC pad. In order to deal with the switching noise that is generated in accordance with an increased speed of the LSI, the package board of the related art employs a multilayer substrate, and the power supply plane and the ground plane are disposed next to each other alternately. With this, the switching noise is decreased. For further decreasing the switching noise, a chip capacitor with a high capacity is also mounted on the package board.
FIG. 5 is a cross section for showing the state of the power-supply and ground planes of the package in the vicinity of the capacitor mount area in the case where the chip capacitor is mounted. FIG. 6 is a circuit block diagram for showing the electrical action (however, the interlayer capacity between the third and fourth layers is not shown in FIG. 6). The chip capacitor 224 is connected to a power-supply-side pad 214 and a ground-side pad 215, which are provided on the first layer. The power-supply-side pad 214 is connected to the power supply plane 202 of the third layer through the interlayer connecting conductor 209h, and the ground plane 203 to which the ground-side pad 215 is provided is connected to a ground plane 204 of the fourth layer through the interlayer connecting conductor 209e. Therefore, the chip capacitor 224 is parallel-connected to the interlayer capacity between the third and fourth layers. The power supply plane 202 is connected to the power-supply FC pad 207 through the interlayer connecting conductor 209b, and the ground plane 204 is connected to the ground FC pad 206 through the interlayer connecting conductor 209a. By adjacently disposing the power supply plane and the ground plane in this manner and, in addition, by providing the chip capacitor, the switching noise has been decreased.
However, when the ground plane 203 of the first layer and the ground FC pad 206 are disconnected, the both are connected to each other through the ground plane 204 and the interlayer connecting conductors 209a, 209e, which are provided on another wiring layer. Thus, there generates inductance components La and Le of the interlayer connecting conductors parasitically between the ground side of the interlayer connecting capacity 1-3 of the first to third layers and the ground FC pad 206, and between the ground-side terminal of the chip capacitor 224 and the ground FC pad 206. As described, there are the inductance components La, Le of the interlayer connecting conductors for connecting the ground plane present in a position that is closer to the LSI chip 221 than the capacity C cap of the chip capacitor 224 and the interlayer capacities C1-C3 of the first to third layers. Therefore, it offsets the effect of the interlayer capacities C1-C3 and the chip capacitor 224 for absorbing the switching noise.